Vhdl Modeling for Digital Design Synthesis (Reprint)

The purpose of this book is to introduce VHSIC Hardware Description Lan­ guage (VHDL) and its use for synthesis. VHDL was originally introduced as a hardware description language that per­ mitted the simulation of digital designs. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum.